Sigma Delta A/D and D/A converters that employ multi-level DACs have numerous advantages over those using single bit. Increased stability, more aggressive noise transfer function and the additional quantizer bits lead to a large increase in the SNR performance. In addition, the requirements of any reconstruction filter following a multi-bit DAC is significantly relaxed when compared to single bit. For converters with multi-bit quantizers, the linearity of the DAC must match or exceed that of the overall converter to avoid degradation of the signal. Achieving high levels of linearity requires strict matching of the analog components; in practice matching of these analog components is limited by systematic and random effects that occur during circuit fabrication.
Implementing sigma delta and oversampling converters in the continuous time domain offer several advantages over the discrete time equivalent. In the case of continuous time sigma delta ADCs, the loop filter can be implemented using continuous time integrators; these can act as an anti-aliasing filter removing the need for additional filtering. In discrete time digital to analog converters, the switched capacitor analog reconstruction filter required at the output is limited by kT/C noise. However, moving to a continuous time implementation avoids this limitation. While continuous time solutions offer many advantages over discrete time implementations, it is important to note they require a continuous time DAC. This means that in addition to the amplitude mismatch error, mismatches in the rise and fall times of the DAC elements switching ‘on’ and ‘off’ lead to another error source known as Inter Symbol Interference (ISI).
Mismatch error is the process whereby random and systematic errors occur during the fabrication of the DAC elements. When the DAC elements are summed to form the DAC output, these errors appear as noise and distortion at the output. ISI error occurs due to a mismatch between the rise and fall times of the DAC elements. This leads to a process by which the current value of a DAC element is affected by the previous value of the element. This altering of element values results in distortion at the output of the DAC. Like mismatch error, ISI error reduces the DACs ability to convert a signal faithfully by adding noise and distortion at the output.
Conventional solutions to reduce inter symbol interference (ISI) error involve the use of DAC coding schemes namely return to zero (RTZ) and dual return to zero (DRTZ), as disclosed in N. Khiem, R. Adams, and K. Sweetland, “A 113 dB SNR oversampling sigma-delta DAC for CD/DVD application,” Consumer Electronics, IEEE Transactions on, vol. 44, pp. 1019-1023, 1998. In RTZ, the output of the digital to analog converter (DAC) is returned to zero at each conversion cycle; while this mitigates the ISI error, the scheme is very sensitive to clock jitter and introduces sharp transitions in the DAC output which have to be filtered by the subsequent circuitry. The DRTZ scheme uses two sub RTZ DACs operating in parallel, their outputs which are 180 degrees out of phase are summed together to form a single DAC output. Unlike RTZ coding, DRTZ maintains the DAC output amplitude and avoids the sharp transitions and increased clock jitter sensitivity. Although this scheme eliminates the ISI error, it requires twice the number of DAC elements and an accurate clocking scheme.
An analog based solution to ISI error was proposed in N. Khiem, A. Bandyopadhyay, B. Adams, K. Sweetland, and P. Baginski, “A 108 dB SNR, 1.1 mW Oversampling Audio DAC With A Three-level DEM Technique,” Solid-State Circuits, IEEE Journal of, vol. 43, pp. 2592-2600, 2008; in this method the settled output of the DAC is sampled using a track and hold circuit. This effectively avoids the ISI error, but the solution requires additional analog sampling circuitry and can introduce the problem of aliasing of high frequency noise into the signal band.
In S. Tao, R. Schreier, and F. Hudson, “Mismatch shaping for a current-mode multibit delta-sigma DAC,” Solid-State Circuits, IEEE Journal of, vol. 34, pp. 331-338, 1999 a Modified Mismatch Shaper (MMS) is presented, the authors use a dynamic element matching (DEM) scheme where the number of elements switching ‘on’ and ‘off’ is set to a constant value; this has the effect of turning the ISI error into a DC offset. The drawback of this technique is that it places a restriction limiting the output range of the modulator.
In J. De Maeyer, P. Rombouts, and L. Weyten, “Addressing static and dynamic errors in bandpass unit element multibit DAC's,” in Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on, 2004, pp. I-345-I-348 Vol. 1 and J. De Maeyer, P. Rombouts, and L. Weyten, “Addressing static and dynamic errors in unit element multibit DACs,” Electronics Letters, vol. 39, pp. 1038-1039, 2003; the authors present a DEM algorithm which ensures that DAC elements cannot be used for consecutive conversion cycles. While this method is effective at mitigating the mismatch error, it requires twice the number of DAC elements and hence is a sub-optimal use of the available redundancy.
In L. Risbo, R. Hezar, B. Kelleci, H. Kiper, and M. Fares, “Digital Approaches to ISI-Mitigation in High-Resolution Oversampled Multi-Level D/A Converters,” Solid-State Circuits, IEEE Journal of, vol. 46, pp. 2892-2903, 2011 and L. Risbo, R. Hezar, B. Kelleci, A. Bjoern-Josefsen, “Shaping inter-symbol-interference in sigma-delta converter”, US patent 2011/0267210, the authors present a DEM scheme that combines ISI and mismatch error shaping. This scheme seeks to shape the mismatch error by using the element usage history and the ISI error by filtering the element transition density. While this scheme provides an improvement over the state of the art, it suffers from tonal distortion as the input signal amplitude increases due to its inability to directly control the number of element transitions during each DAC conversion cycle. In A. Sanyal, L. Chen, and N. Sun, “Dynamic Element Matching With Signal-Independent Element Transition Rates for Multibit ΔΣ Modulators,” Circuits and Systems I: Regular Papers, IEEE Transactions on, vol. 62, pp. 1325-1334, 2015, the authors present a mismatch shaping technique that controls the number of element transitions so that they are independent of the input signal. The scheme allows the instantaneous number of transitions to vary among three adjacent integers L±1 so that they are no longer correlated with the input signal. A noise shaping loop chooses the number of transitions from these adjacent integers resulting in the ISI error being shaped. This scheme improves state of the art, however the ISI shaping produces tonal distortion for which dither logic is required to remove.
It is therefore an object to provide a system and method to solve the problem of Inter Symbol Interference (ISI) and mismatch error in a data converter.